Sun Previews New UltraSPARC IIIi Processor
Sun Microsystems previewed a new branch of the UltraSPARC III microprocessor family tree optimized for high density one-to-four processor server and workstation systems. Technical highlights for the chip include large L1 and L2 on-chip memory caches, integration of Sun's JBUS interconnect, and the first-ever use of asynchronous logic technology developed at Sun Microsystems Laboratories in the processor's memory interface subsystem. Sun Microsystems previewed a new branch of the UltraSPARC III microprocessor family tree optimized for high density one-to-four processor server and workstation systems. Technical highlights for the chip include large L1 and L2 on-chip memory caches, integration of Sun's JBUS interconnect, and the first-ever use of asynchronous logic technology developed at Sun Microsystems Laboratories in the processor's memory interface subsystem.
"We designed the UltraSPARC IIIi processor to address a one-to-four way multiprocessing sweet spot. The chip is intended to reduce system costs by integrating previously off-chip subsystems on chip, thereby simplifying system design and reducing part counts. The JBUS interface in particular simplifies design of small scale multiprocessor systems by implementing a fast 'goo-less logic' interconnect between processors," said Sun's Kevin Normoyle, in a technology disclosure presentation delivered at the 2001 Microprocessor Forum. "Also, by executing the processor on a new Texas Instruments' 0.13 micron, copper interconnect process, we expect to introduce the chip at a more than 1 GHz, clock speed, while keeping power consumption below 60 Watts, an important spec for systems for easy-deployment, high-compute density systems."
The UltraSPARC IIIi design is based on an UltraSPARC III supplemented with an enhanced set of on-chip features that position the device for design into cost-optimized, high performance one- to four-way multiprocessing systems. Significant new on-chip elements integrated into the UltraSPARC IIIi processor design include:
- 1 Megabyte, four-way associative L2 cache memory
- Large data and instruction TLB (Translation Look-Aside Buffer) that support a variety of page sizes from 8 KByte to 4 MByte
- DDR (Double Data Rate) memory interface, 266 MHz at 16-bits wide, controlling up to 16 GBytes per processor
- First use of the sun JBUS interconnect technology
Even though the UltraSPARC IIIi design will integrated three times as many transistors (87 Million) as the UltraSPARC III (29 Million), the UltraSPARC IIIi is expected to dissipate less than 60 Watts of power. In addition, the design will incorporate low-power consumption operation modes to further reduce power consumption under light loading. The low peak power figure derives largely through fabricating the chip on a new 0.13 micron, seven-layer metal, copper interconnect, low-K dielectric process available to Sun at Texas Instruments.
The UltraSPARC IIIi processor design also marks the world's first integration of elements of asynchronous logic technology developed at Sun Microsystems Laboratories. The processor's memory controller includes asynchronous logic-based first-in, first-out (FIFO) circuits in the memory controller input/output section to absorb clock skew variations inherent in tens-of-million transistor class chips. Although the asynchronous FIFO is a small part of the UltraSPARC IIIi processor's overall design, it is another instance of technology transfer from Sun Labs influencing the company's product designs.
Product Availability and Roadmap
In line with this presentation's status as technology disclosure, Sun did not announce a time table for introduction of the UltraSPARC IIIi processor either on its own as an OEM product or as an element in Sun's system products.
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