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Intel Revs Up Montecito

By Amy Newman (Send Email)
Posted Nov 14, 2003


Intel Friday unveiled the latest enhancements for its Montecito rev of the Itanium 2 processor. Slated for a 2005 release, the new chip will offer multithreaded and multicore processing, and 24 MB of L3 Cache, Lisa Hambrick Graff, Director, Itanium 2 Worldwide Ramp, told ServerWatch.

Intel Friday unveiled the latest enhancements for its Montecito rev of the Itanium 2 processor. The new chip will offer multithreaded and multicore processing as well as 24 MB of L3 Cache.

The current version (Madison) of the chip offers 6 MB of L3 cache.

Montecito will contain more than 1 billion transistors on a single chip, making it the most dense chip Intel has developed, to date, Graff said. It will also feature 90 nanometer process technology and, like its predecessor, will be compatible with other Itanium-2-based systems.

The downside of having so many cores so close together is that a bottleneck to memory can occur, rendering speed developments meaningless. To prevent this, Intel has "kept the data on the processor and off of memory," Graff said. As a result, the Tanglewood generation (the successor to Montecito) of Itanium 2 will have achieved a seven-fold jump in performance over the initial release.

Kevin Krewell, senior analyst for In-Stat/MDR, told ServerWatch that this announcement "highlights an important trend in server processor designs: chip-level multiprocessing. The addition of multithreading to the Itanium cores is a pretty major accomplishment this soon. The Itanium core has a very large set of registers that need to be considered in adding multithreading. With two, dual-threaded cores, the Montecito processor will look like four processors to software."

In addition, "If Intel can deliver Montecito in 2005, it will have an edge over Sun's UltraSPARC IV which is dual core, but each core is single-threaded. Intel believes that this is part of its proof that the Itanium architecture is as scalable, if not more scalable, as RISC processors (such as SPARC and IBM's Power)," Kewell said.

Although this addition is a big step for Intel, it is not a revolutionary concept to the processor world. Krewell cautioned, "IBM's Power 5 will have a two, dual-threaded cores on one die and it's expected to ship in systems in 2004. So Intel is still behind IBM but may catch up to Sun in 2005."

Itanium 2's penetration has come hard and fast, Graff said. She credits Windows 2003 Server as the "catalyst" for ISVs to develop Itanium-optimized solutions. With the release of the new operating system and the necessary porting that would accompany it, many vendors chose to port across the board (and optimize their apps for Itanium) at this time.

In June, prior to Window Server 2003's release, only 400 applications were optimized for Itanium; today there are 1,000, which exceeds Intel's original year-end goal of 700. The vendor has since revised its 1H04 goal to 1,500. Graff said about 65 percent to 70 percent of Itanium-2-based systems are deploying Windows Server 2003, the remainder are deploying Linux.

In terms of hardware wins, Graff said that Intel is "winning mostly against RISC." She estimates about the largest percentage of wins -- 35 percent -- come from Sun. She also attributes HP's migrations and Xeon upgrades to the growth. IDC forecasts that about 100,000 Itanium-based systems will be sold in 2004, and about 300,000 in 2005, thus exceeding volumes of traditional RISC architectures. In addition, 8 out of 9 RISC vendors now offer Itanium 2 processor-based platforms, Graff said.

In recent weeks, Intel has seen a large influx in Itanium deployments on midrange systems, particularly in the 8-way to 16-way space, Graff said. Vendors incorporating Itanium 2 into their product lines range from IBM and HP, to SGI, to a number of second- and third-tier vendors.

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