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Full-Chip, Transistor-Level Parasitic Extraction for SoC Designs

By Wayne Kawamoto (Send Email)
Posted Aug 27, 2002


Full-Chip, Transistor-Level Parasitic Extraction for SoC Designs Mentor Graphics Corporation announced the availability of its Calibre xRC, a full-chip, transistor-level parasitic extraction tool. According to the company, Calibre xRC, which runs on Solaris, addresses the performance and accuracy requirements of today's most complex analog mixed-signal (AMS) system-on-chip (SoC) designs. Mentor Graphics Corporation announced the availability of its Calibre xRC, a full-chip, transistor-level parasitic extraction tool. According to the company, Calibre xRC, which runs on Solaris, addresses the performance and accuracy requirements of today's most complex analog mixed-signal (AMS) system-on-chip (SoC) designs.

Mentor Graphics Corporation announced the availability of its Calibre xRC, a full-chip, transistor-level parasitic extraction tool. According to the company, Calibre xRC addresses the performance and accuracy requirements of today's most complex analog mixed-signal (AMS) system-on-chip (SoC) designs.

The company says that with Calibre xRC, Mentor extends the core Calibre technology to address the requirements of AMS SoC parasitic extraction. Calibre xRC is designed to combine the proven performance, capacity and hierarchical geometry processing of the Calibre hierarchical engine with the accuracy and layout vs. schematic (LVS) integration of xCalibre.

According to the company, parasitic extraction tools are customized to handle the requirements of a specific design flow. This specialization forces SoC designers to either maintain multiple tools or use functionality that is unsuitable for a variety of design styles. Unlike other tools, Calibre xRC was designed to deliver extraction technology in a single tool for the full range of design styles found in AMS SoC designs (analog, memory, full custom, etc).

Today's AMS SoC designs can fail if the parasitic effects of passive interconnects are not properly addressed. These effects are not only becoming significant for timing, but also for power, reliability, and noise. Detailed analysis of these effects requires much more than a traditional extracted SPICE netlist or timing file. AMS SoCs require a comprehensive approach to parasitic extraction, including:

  • accurate extraction algorithms to model interconnect effects on advanced processes.
  • tight integration into the design environment to ensure efficient data handling for both upstream, design creation environments, and downstream post-layout analysis.
  • advanced data management to handle the enormous amount of parasitic elements that are extracted from current SoC designs.

Pricing and Availability
Calibre xRC is currently in beta evaluation with first customer ship planned for Q3, 2002. Calibre xRC runs on Solaris, HP and Linux. Moew information is available on Mentor Graphics' Web site.

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